perf: add native AVX2 uint64/int64 mul kernel#1306
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DiamonDinoia merged 1 commit intoxtensor-stack:masterfrom Apr 16, 2026
Merged
perf: add native AVX2 uint64/int64 mul kernel#1306DiamonDinoia merged 1 commit intoxtensor-stack:masterfrom
DiamonDinoia merged 1 commit intoxtensor-stack:masterfrom
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Previously batch<[u]int64_t, avx2> mul fell through to AVX, which has no integer mul, which in turn fell through to SSE4.1 — splitting each 256-bit register into two 128-bit halves (vextracti128/vinserti128) and running the mul_epu32 sequence twice. Add a sizeof(T)==8 specialization using _mm256_mul_epu32 directly, mirroring the SSE4.1 pattern with 256-bit intrinsics. Generates 8 ymm ops: 2 vpshufd, 3 vpmuludq, 2 vpaddq, 1 vpsllq — no lane splitting. AVX512F (without DQ) also benefits since it forwards to the AVX2 kernel.
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@serge-sans-paille this is a small one :) |
Contributor
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yep, looks good! |
serge-sans-paille
approved these changes
Apr 16, 2026
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You should ahve the right to merge now, feel free to do so once green. |
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Previously batch<[u]int64_t, avx2> mul fell through to AVX, which has no integer mul, which in turn fell through to SSE4.1 — splitting each 256-bit register into two 128-bit halves (vextracti128/vinserti128) and running the mul_epu32 sequence twice.
Add a sizeof(T)==8 specialization using _mm256_mul_epu32 directly, mirroring the SSE4.1 pattern with 256-bit intrinsics. Generates 8 ymm ops: 2 vpshufd, 3 vpmuludq, 2 vpaddq, 1 vpsllq — no lane splitting.
AVX512F (without DQ) also benefits since it forwards to the AVX2 kernel.