riscv64 fails to build Python/perf_jit_trampoline.c: Unsupported target architecture

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build: https://buildbot.python.org/all/#/builders/1379/builds/625

gcc -c -fno-strict-overflow -fstack-protector-strong -Wtrampolines -Wsign-compare -DNDEBUG -g -O3 -Wall    -std=c11 -Wextra -Wno-unused-parameter -Wno-missing-field-initializers -Wstrict-prototypes -Werror=implicit-function-declaration -fvisibility=hidden  -I./Include/internal -I./Include/internal/mimalloc  -I. -I./Include    -DPy_BUILD_CORE -o Python/perf_trampoline.o Python/perf_trampoline.c
gcc -c -fno-strict-overflow -fstack-protector-strong -Wtrampolines -Wsign-compare -DNDEBUG -g -O3 -Wall    -std=c11 -Wextra -Wno-unused-parameter -Wno-missing-field-initializers -Wstrict-prototypes -Werror=implicit-function-declaration -fvisibility=hidden  -I./Include/internal -I./Include/internal/mimalloc  -I. -I./Include    -DPy_BUILD_CORE -o Python/perf_jit_trampoline.o Python/perf_jit_trampoline.c
Python/perf_jit_trampoline.c:375:6: error: #error "Unsupported target architecture"
  375 | #    error "Unsupported target architecture"
      |      ^~~~~

• Latest successful build: https://buildbot.python.org/all/#/builders/1379/builds/551 -- commit 69b3e8e
• First failing build: https://buildbot.python.org/all/#/builders/1379/builds/553 -- commit 56657f6

cc @pablogsal

Linked PRs

• gh-121201: Disable perf_trampoline on riscv64 for now #121328
• [3.13] gh-121201: Disable perf_trampoline on riscv64 for now (GH-121328) #121336
• gh-121201: Support riscv64 architecture for Perf JIT #121387

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cc @furkanonder

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configure says:

checking for the platform triplet based on compiler characteristics... riscv64-linux-gnu

checking perf trampoline... yes

[pablogsal]

Hummm, looks like we are missing the definitions for the registers for riscv64 here:

cpython/Python/perf_jit_trampoline.c

Lines 352 to 376 in af8c3d7

	#ifdef __x86_64__
	/* Yes, the order is strange, but correct. */
	DWRF_REG_AX,
	DWRF_REG_DX,
	DWRF_REG_CX,
	DWRF_REG_BX,
	DWRF_REG_SI,
	DWRF_REG_DI,
	DWRF_REG_BP,
	DWRF_REG_SP,
	DWRF_REG_8,
	DWRF_REG_9,
	DWRF_REG_10,
	DWRF_REG_11,
	DWRF_REG_12,
	DWRF_REG_13,
	DWRF_REG_14,
	DWRF_REG_15,
	DWRF_REG_RA,
	#elif defined(__aarch64__) && defined(__AARCH64EL__) && !defined(__ILP32__)
	DWRF_REG_SP = 31,
	DWRF_REG_RA = 30,
	#else
	# error "Unsupported target architecture"
	#endif

@furkanonder can you take a look? Otherwise we may need to deactivate RISKV64 support meanwhile we figure out the DWARF definitions.

[pablogsal]

I think it may be enough to add riskv here:

cpython/Python/perf_jit_trampoline.c

Line 371 in af8c3d7

#elif defined(__aarch64__) && defined(__AARCH64EL__) && !defined(__ILP32__)

but I am not sure about the numbers. It seems that they match the aarch64 but I would need a riskv machine to try out.

[pablogsal]

I way to try out the numbers is to generate DWARF in riskv for the same function and check the numeric values of DWRF_REG_SP and DWRF_REG_RA

[pablogsal]

Deactivated for now in ##121328