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Use SIMD operations in InitBlkUnroll/CopyBlkUnroll and increase unroll limit up to 128 bytes #61030

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Merged
echesakov merged 16 commits into from
Dec 28, 2021
Merged

Use SIMD operations in InitBlkUnroll/CopyBlkUnroll and increase unroll limit up to 128 bytes #61030

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2e26efa
Use SIMD operations in CodeGen::genCodeForInitBlkUnroll()
echesakov Nov 10, 2021
d652014
Use SIMD operations in CodeGen::genCodeForCpBlkUnroll()
echesakov Nov 10, 2021
c3566b1
Remove restrictions on offset in Lowering::ContainBlockStoreAddress()
echesakov Dec 2, 2021
c7d9d08
Remove unused macros in src/coreclr/jit/instr.h
echesakov Dec 21, 2021
52e22d7
Rename FPbased -> fpBased in src/coreclr/jit/codegenarmarch.cpp
echesakov Dec 16, 2021
c9be2de
Split Arm32 and Arm64 logic around srcReg in CodeGen::genCodeForInitB…
echesakov Dec 16, 2021
e7cff76
Change int -> unsigned for InstrCount in CountingStream in src/corecl…
echesakov Dec 16, 2021
fb143b0
Change int -> unsigned for InstrCount in InitBlockUnrollHelper and Co…
echesakov Dec 16, 2021
9eb1f85
Allocate an integer register in LSRA instead of relying on rsGetRsvdR…
echesakov Dec 17, 2021
ad771d3
Allocate an integer register in LSRA instead of relying on rsGetRsvdR…
echesakov Dec 17, 2021
fbee8d6
Change int -> unsigned for regSizeBytes in src/coreclr/jit/codegenarm…
echesakov Dec 20, 2021
dbc75b5
Move encoding-related logic to the emitter - add emitter::canEncodeLo…
echesakov Dec 21, 2021
dcf0799
Re-structure Streams and Helpers and describe the design in src/corec…
echesakov Dec 21, 2021
8eabe6b
Re-structure CodeGen::genCodeForInitBlkUnroll() in src/coreclr/jit/co…
echesakov Dec 16, 2021
96ee5bf
Re-structure CodeGen::genCodeForCpBlkUnroll() in src/coreclr/jit/code…
echesakov Dec 21, 2021
e457e92
Change how LSRA allocates int/SIMD registers when both srcAddr/dstAdd…
echesakov Dec 23, 2021
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